- 几个好的参考材料 (4 篇回复)
- [book] Verilog HDL Engineer Training Book, from VIA (3 篇回复)
- RTL编码指南 (6 篇回复)
- VLSI-SoC Research Trends in VLSI and Systems on Chip (1 篇回复)
- [paper]设计异步多时钟系统的综合以及描述技巧 (1 篇回复)
- synopsys DC 2007.03 workshop (2 篇回复)
- 发书的太多,多交流吧 (2 篇回复)
- LowPowerDesignGuide (4 篇回复)
- [book] Springer - SystemVerilog for Verification, 2nd Edition (5 篇回复)
- verilog2001 (0 篇回复)
- Top 10 methods for ASIC power minimization (4 篇回复)
- [doc]ARMv6 Architecture (5 篇回复)
- Clock Generators for SOC (1 篇回复)
- VMM-LP (1 篇回复)
- [book] Digital Systems Testing and Testable Design (11 篇回复)
- The Transaction Level Modeling standard of the Open SystemC Initiative (OSCI) (0 篇回复)
- ADVANCES IN DESIGN AND SPECIFICATION LANGUAGES FOR SOCS (0 篇回复)
- carry save addition (0 篇回复)
- Advanced ASIC Chip Synthesis 2nd (0 篇回复)
- coding_guidelines_for_datapath synthesis (0 篇回复)
- ASYNCHRONOUS_CIRCUIT_DESIGN_--_A_CASE_STUDY_OF_A_FRAMEWORK_CALLED_ACK (0 篇回复)
- [book]MIT.Press.Circuit.Design.With.VHDL.eBook-TLFeBOOK (0 篇回复)
- 9异步设计的经典书籍 (0 篇回复)
- [paper] Reducing Branch Delay to Zero in Pipelined Processors.pdf (0 篇回复)
- Asynchronous_system_on_chip (0 篇回复)
- [book] SystemVerilog for Design Second Edition (1 篇回复)
- [book] Finite State Machine Datapath Design, Optimization, and Implementation (0 篇回复)
- [book] Complete Digital Design (0 篇回复)
页:
[1]