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全局置顶 隐藏置顶帖 论坛的等级制度(以及论坛下载说明) [2009年12月7日更新] attach_img digest  ...2345 henryxu 2007-6-15 123108287 mlbqayyu 2019-1-20 11:47
全局置顶 隐藏置顶帖 招募版主[2011-05-15更新],不求技术NB,只求对技术有兴趣!  ...234 ic.expert 2009-12-5 9966547 mnjkc 2018-8-11 21:58
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a practical guide to adopting the universal verfication methodology attachment wangyukan 2015-1-29 23383 mlbqayyu 2019-1-20 11:16
UVM1.1应用指南及源代码分析_20111211版 attachment 越光飞扬 2013-9-5 13516 uye2364 2018-10-24 10:14
Design Compiler User Guide attachment waterbird_eda 2014-8-10 25198 xenostt 2018-5-11 09:00
来自candece的UVM脚本生成器(Simple UVM 1.1 UVC template generator - v1.10 attachment 深度验证 2012-1-25 14797 hjacky 2017-5-19 14:03
请问systemverilog中dist分配的权重怎么计算 jkdgf 2015-7-1 24200 wangyangsdu 2016-9-24 12:27
OVM源代码分析之sequence机制 attachment digest agree  ...2 深度验证 2010-4-18 3120384 荆棘鸟 2015-10-14 17:00
Systemverilog Functional Coverage(SV功能覆盖入门教程) attach_img ic.expert 2011-8-9 29459 huanghx 2015-6-5 22:28
Cadence数字后端教程.rar attachment waterbird_eda 2014-8-10 14102 xuleo 2015-5-20 12:36
[user guide]UVM1.1 user guide attachment leobeyondygj 2011-10-14 24674 Pirate0320 2015-1-9 21:31
[book] Standardized Functional Verification(RTL功能验证的标准流程) attachment 深度验证 2012-2-20 410463 loveayu1986 2014-11-10 09:01
Vim(GVim)的Systemverilog和OVM的语法高亮显示 attachment 深度验证 2010-4-2 1016772 似水如烟 2014-11-6 17:09
SV能像V一样debug吗? attachment LAUREN 2010-9-6 710211 lianhuo 2014-9-15 15:25
DC教程 attachment waterbird_eda 2014-8-10 03102 waterbird_eda 2014-8-10 16:29
Calibration tech attachment waterbird_eda 2014-8-10 02874 waterbird_eda 2014-8-10 16:27
AIC_project.pdf attachment waterbird_eda 2014-8-10 02942 waterbird_eda 2014-8-10 16:25
Advanced Design for Low Power attachment waterbird_eda 2014-8-10 02865 waterbird_eda 2014-8-10 16:24
版图设计讲稿 attachment waterbird_eda 2014-8-10 02516 waterbird_eda 2014-8-10 16:20
65nm_Signoff.pdf attachment waterbird_eda 2014-8-10 02713 waterbird_eda 2014-8-10 16:19
Calibre_xRC的使用.pdf attachment waterbird_eda 2014-8-10 02341 waterbird_eda 2014-8-10 16:17
CMOS集成电路的IO设计 attachment waterbird_eda 2014-8-10 02587 waterbird_eda 2014-8-10 16:13
SystemVerilog——任务和函数(Tasks and Functions) ic.expert 2011-7-19 113991 watercube 2014-4-23 10:12
谈谈验证中的SystemVerilog和CPP ic.expert 2011-8-11 1017009 刘川 2013-11-9 13:12
RTL cedric761193 2012-4-11 14423 刘川 2013-11-9 12:38
新创公司实现八星期完成SoC设计里程碑 69350 2012-4-25 86661 刘川 2013-11-9 12:36
DDR端口时序约束和时序分析guide attachment agree sirc 2010-2-7 911518 loveayu1986 2013-10-6 20:19
ADVANCED ASIC CHIP SYNTHESIS.ppt attachment qazwsxedc 2010-5-23 76680 loveayu1986 2013-10-6 19:58
静态时序分析失败 chinahhucai 2013-7-13 13274 arthur_wang_orz 2013-7-31 17:24
Systemverilog编辑器,有自动补全atuo-complete和代码定义查看功能 digest ic.expert 2011-8-8 1517944 wanderhao 2013-7-15 13:38
[2012新书][Cadence UVM教材]Advanced Verification Topics 深度验证 2012-2-19 511688 tedazsx 2013-6-18 21:26
[book] A Practical Guide to Adopting the Universal Verification Methodology(UVM) attach_img ic.expert 2011-7-16 2720761 gstart 2013-6-6 10:53
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