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[招聘] 【英伟达NVIDIA上海】招聘高级芯片验证工程师/验证工程师

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发表于 2018-3-12 09:57:05 | 显示全部楼层 |阅读模式
工作地点: 上海市浦东新区秋月路26号     
投递邮箱:heatherl@nvidia.com     

高级芯片验证工程师Senior Verification Engineer

工作职责:
  • You will participate in theresearch of verification methodology to improve automation and productivity toproduce Nvidia’s new high-quality state of the art products.
  • Read IAS and design specs tounderstand the design requirement and build corresponding testplan. Review thetestplan with arch/design engineers.
  • You responses to build block/IP testbenchbased on UVM methodology.
  • The responsibilities includesbuilding test run and regression flow. Triage failures in regression and helpdesigner root cause the bug.
  • Work includes Build variousmetrics (passing rate, functional coverage, etc) and monitor its health.
  • Take SOC verification on fullchiptest environment for IPs
  • Analyse functional/code coverageresult and identify the coverage holes. Work with design engineer to improvethe coverage score.
  • Deploy the advanced verificationmethodology and infrastructure of the SOC/IP

任职资格:
  • BS / MS in electrical / computerengineering and related.
  • 3+ years (MS) or 5+ years (BS)working experience.
  • Familiar with advance verificationmethodology (UVM, VMM, OVM, etc), tools and flow
  • Fully experienced verificationflow, including testplan, test, coverage model, testbench, BFM modeling.
  • Deep understanding in Verilog andHVL (High-level Verification Language)

加分项:
  • Strong programming skills in Perland C/C++is plus
  • Having good arch/design experienceis big plus.
  • At least good at one of the scriptprograming lanange : Perl, Shell, Ruby, Python, etc.
  • Fluent English (both written andspoken) and excellent communication skills
  • Proven ability to workindependently as well as in a multi-disciplinary group environment
  • Strong analytical skills

芯片验证工程师ASIC Verification Engineer (Clocks)

工作职责:
  • Module-level or Chip-level logicdesign, synthesis, timing constraints, and silicon bring-up.
  • Module-level or Chip-levelverification, both for function and test mode
  • Methodology or Flow developmentfor above tasks.

任职资格:
  • BS / MS in electrical / computerengineering and related.
  • Understand ASICdesign/verification/implementation flow
  • Familiar with design/verificationlanguages as C/C++, Verilog or VHDL
  • Know industrial standard scriptinglanguage as Perl, or Python, TCL, Ruby
  • Excellent analytical andproblem-solving skills
  • Fluent English and excellentcommunication skills
  • Good team work spirit, easy tocooperate with team members

加分项:
  • Understand JTAG, DFT, or OCC is a plus

工作地点: 上海市浦东新区秋月路26号      
投递邮箱:heatherl@nvidia.com   


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