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ESL综合之C-to-Verilog 免费工具(新手必看 )

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发表于 2010-10-1 11:11:19 | 显示全部楼层 |阅读模式

 

C-to-Verilog is a free on-line C to Verilog compiler. You can copy-and-paste your existing C code and our on-line compiler will synthesize it into optimized verilog.


For additional information on how to use our website to create the best FPGA designs, watch the screencast below.

 

C-to-Verilog provides a free on-line service which allows users to compile their existing C code into optimized Verilog code. This code can be synthesized into an FPGA or ASIC.


Automating hardware designs can reduce verification time and cost. Our tools enable the development of embedded system-on-chip and integrate with design tools such as Xilinx EDK. We provide this service to demonstrate our technology. We believe that we outperform other competitors. The implementation of the synthesis system is described in the research page.

 

 

 

请访问以下链接!(如果访问不了请翻墙{:4_203:} )

 

http://www.c-to-verilog.com/online.html

 

 

 

 

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发表于 2010-12-28 22:39:37 | 显示全部楼层
现在已经上不去了,被和谐了吗?
发表于 2010-12-30 19:01:31 | 显示全部楼层
The coding style is not using the recommended way.
发表于 2010-12-31 21:59:19 | 显示全部楼层
悲剧。。。上不去了。请问有哪款商用软件有类似的功能吗?
发表于 2011-2-17 18:32:38 | 显示全部楼层
可以上去,但是产的.v文件感觉不是很好……还是自己写为好。:)
发表于 2011-4-16 19:52:31 | 显示全部楼层
产生出来敢随便用在项目里吗
发表于 2011-7-14 12:00:14 | 显示全部楼层
回复 ic.expert 的帖子

對單一演算函數或方法之設計較有利
不利架構設計
发表于 2011-7-17 05:25:59 | 显示全部楼层
我想主要差異在未能使用Precision RTL元件來規範輸出的verilog語法,因此讓輸出之verilog與RTL間有相當大的差異,所以可能在邏輯上就無法確定verilog是否能用
當然最好能配置Device Model,再規範RTL元件, 於C之語法中需要交代Interface邏輯,如此就可以得到期盼中的C2V
发表于 2011-8-18 15:46:14 | 显示全部楼层
这个就算了吧,我还是相信商业化的产品
PICO, Catapult, AutoESL
发表于 2011-12-21 22:22:09 | 显示全部楼层
You can download the code and rewrite: http://c-to-verilog.com/code.zip
发表于 2012-3-23 16:07:39 | 显示全部楼层
Perfect! Very interesting!
发表于 2018-4-28 16:34:54 | 显示全部楼层
顶......叹为观止.....












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